module float_div (
	clock,
	dataa,
	datab,
	result);

	input	  clock;
	input	[31:0]  dataa;
	input	[31:0]  datab;
	output reg [31:0]  result;
  
	wire aclr;
	wire clk_en;

	assign
		aclr = 1'b0,
		clk_en = 1'b1;



//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  wire_cmpr2_alb = dataa[22:0] < datab[22:0];

	wire a_is_infinity_w = (exp_a_all_one_w & (~ man_a_not_zero_w));
	wire a_is_nan_w = (exp_a_all_one_w & man_a_not_zero_w);
	wire a_zero_b_not = (exp_b_not_zero_w & (~ exp_a_not_zero_w));
	wire b_is_infinity_w = (exp_b_all_one_w & (~ man_b_not_zero_w));
	wire b_is_nan_w = (exp_b_all_one_w & man_b_not_zero_w);
	wire exp_a_all_one_w = &dataa[30:23];
	wire exp_a_not_zero_w = |dataa[30:23];
	wire exp_b_all_one_w = &datab[30:23];
	wire exp_b_not_zero_w = |datab[30:23];
	wire  [8:0]  exp_sub_a_w = {1'b0, dataa[30:23]};
	wire  [8:0]  exp_sub_b_w = {1'b0, datab[30:23]};
	wire [22:0]  man_a_dffe1_wi = dataa[22:0];
	wire man_a_not_zero_w = |dataa[22:0];
	wire [22:0]  man_b_dffe1_wi = datab[22:0];
	wire man_b_not_zero_w = |datab[22:0];

wire [8:0] wire_altsyncram3_q_a;
float_div_table float_div_table_inst(
  .in(datab[22:14]),
  .out(wire_altsyncram3_q_a)
);

reg  [8:0] reg_exp_sub_result;
reg	frac_a_smaller_dffe1;
reg	[22:0]	man_b_dffe1_dffe1;
reg [8:0]   altsyncram3_q_a_0;
reg	[22:0]	man_a_dffe1_dffe1;
reg	divbyzero_pipe_dffe_0;
reg	b_is_infinity_dffe_0;
reg	a_is_infinity_dffe_0;
reg	a_zero_b_not_dffe_0;
reg	nan_pipe_dffe_0;
reg	sign_pipe_dffe_0;
reg	both_exp_zeros_dffe;
always @ (posedge clock)begin
  frac_a_smaller_dffe1 <= wire_cmpr2_alb;
  man_b_dffe1_dffe1 <= man_b_dffe1_wi;
  altsyncram3_q_a_0 <= wire_altsyncram3_q_a;
  man_a_dffe1_dffe1 <= man_a_dffe1_wi;
  a_zero_b_not_dffe_0 <= a_zero_b_not;
  b_is_infinity_dffe_0 <= b_is_infinity_w;
  a_is_infinity_dffe_0 <= a_is_infinity_w;
  divbyzero_pipe_dffe_0 <= ((~ exp_b_not_zero_w) & (~ a_is_nan_w) & exp_a_not_zero_w & (~ a_is_infinity_w));
  nan_pipe_dffe_0 <= (a_is_nan_w | b_is_nan_w | (a_is_infinity_w & b_is_infinity_w) | ((~ exp_a_not_zero_w) & (~ exp_b_not_zero_w)));
  sign_pipe_dffe_0 <= (dataa[31] ^ datab[31]);
  reg_exp_sub_result <= exp_sub_a_w - exp_sub_b_w;
  both_exp_zeros_dffe <= ((~ exp_b_not_zero_w) & (~ exp_a_not_zero_w));
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

wire  [8:0]  value_zero_w = {9{1'b0}};
wire  [8:0]  value_normal_w = 9'b001111110;
wire  [8:0]  value_add_one_w = 9'b001111111;

wire	[8:0] wire_select_biasa_dataout = frac_a_smaller_dffe1 ? value_normal_w : value_add_one_w;
wire	[8:0] wire_select_bias_2a_dataout = both_exp_zeros_dffe ? value_zero_w : wire_select_biasa_dataout;
wire	[24:0] wire_man_a_adjusteda_dataout = frac_a_smaller_dffe1 ? {1'b1, man_a_dffe1_dffe1, 1'b0} : {1'b0, 1'b1, man_a_dffe1_dffe1};
wire  [34:0] wire_a1_prod_result;
wire  [33:0] wire_b1_prod_result;
`ifdef isISE
mul25x10u1c   a1_prod( 
  .clk(clock),
  .a(wire_man_a_adjusteda_dataout),
  .b({1'b1, altsyncram3_q_a_0}),
  .p(wire_a1_prod_result)
);
mul24x10u1c   b1_prod( 
  .clk(clock),
  .a({1'b1, man_b_dffe1_dffe1}),
  .b({1'b1, altsyncram3_q_a_0}),
  .p(wire_b1_prod_result)
);
`endif

`ifdef isALTERA
lpm_mult   a1_prod
( 
  .aclr(aclr),
  .clken(clk_en),
  .clock(clock),
  .dataa(wire_man_a_adjusteda_dataout),
  .datab({1'b1, altsyncram3_q_a_0}),
  .result(wire_a1_prod_result)
);
defparam
  a1_prod.lpm_pipeline = 1,
  a1_prod.lpm_representation = "UNSIGNED",
  a1_prod.lpm_widtha = 25,
  a1_prod.lpm_widthb = 10,
  a1_prod.lpm_widthp = 35,
  a1_prod.lpm_type = "lpm_mult",
  a1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";

lpm_mult   b1_prod
( 
  .aclr(aclr),
  .clken(clk_en),
  .clock(clock),
  .dataa({1'b1, man_b_dffe1_dffe1}),
  .datab({1'b1, altsyncram3_q_a_0}),
  .result(wire_b1_prod_result)
);
defparam
  b1_prod.lpm_pipeline = 1,
  b1_prod.lpm_representation = "UNSIGNED",
  b1_prod.lpm_widtha = 24,
  b1_prod.lpm_widthb = 10,
  b1_prod.lpm_widthp = 34,
  b1_prod.lpm_type = "lpm_mult",
  b1_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";

`endif

wire [8:0] a = reg_exp_sub_result;
wire [8:0] b = wire_select_bias_2a_dataout;

wire [8+1:0] temp_sum = a + b;
wire [8:0] sum = temp_sum[8:0];

reg  wire_bias_addition_overflow;
reg  [8:0]   wire_bias_addition_result;
reg	sign_pipe_dffe_1;
reg	nan_pipe_dffe_1;
reg	a_zero_b_not_dffe_1;
reg	a_is_infinity_dffe_1;
reg	divbyzero_pipe_dffe_1;
reg	b_is_infinity_dffe_1;
always @ (posedge clock)begin
  sign_pipe_dffe_1 <= sign_pipe_dffe_0;
  nan_pipe_dffe_1 <= nan_pipe_dffe_0;
  a_zero_b_not_dffe_1 <= a_zero_b_not_dffe_0;
  divbyzero_pipe_dffe_1 <= divbyzero_pipe_dffe_0;
  a_is_infinity_dffe_1 <= a_is_infinity_dffe_0;
  b_is_infinity_dffe_1 <= b_is_infinity_dffe_0;
  wire_bias_addition_overflow <= (~a[8] & ~b[8] & sum[8]) | (a[8] & b[8] & ~sum[8]);
  wire_bias_addition_result <= sum;
  //wire_a1_prod_result
  //wire_b1_prod_result
end


//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
wire [7:0]  underflow_zeros_w = {8{1'b0}};
wire [7:0]  overflow_ones_w = {8{1'b1}};

wire [7:0]  bias_addition_w = wire_bias_addition_result[7:0];
wire exp_add_output_all_one = &bias_addition_w[7:0];
wire exp_add_output_not_zero = |bias_addition_w[7:0];
wire exp_sign_w = wire_bias_addition_result[8];
wire underflow_w = (
    (exp_sign_w ? 1'b1 : (~ exp_add_output_not_zero))
    & (~ wire_bias_addition_overflow)
    & (~ nan_pipe_dffe_1)
    & (~ a_zero_b_not_dffe_1)
    & (~ b_is_infinity_dffe_1)
  );
wire overflow_w = (
  (wire_bias_addition_overflow | ((exp_add_output_all_one & (~ wire_bias_addition_overflow)) & (~ exp_sign_w))) 
  & (~ nan_pipe_dffe_1) 
  & (~ a_is_infinity_dffe_1) 
  & (~ divbyzero_pipe_dffe_1)
);
wire [7:0]  exp_result_w = (
  ({8{((~ wire_bias_addition_overflow) & (~ exp_sign_w))}} & bias_addition_w) 
  | ({8{(((wire_bias_addition_overflow | divbyzero_pipe_dffe_1) | nan_pipe_dffe_1) | a_is_infinity_dffe_1)}} & overflow_ones_w)
);
wire exp_result_mux_sel_w = (
  (
    (a_zero_b_not_dffe_1 | b_is_infinity_dffe_1)
    | (exp_sign_w ? (~ wire_bias_addition_overflow) : ((~ exp_add_output_not_zero) & (~ wire_bias_addition_overflow)))
  )
  & (~ nan_pipe_dffe_1)
);
wire overflow_underflow = (overflow_w | underflow_w);
wire [7:0] wire_exp_result_muxa_dataout = exp_result_mux_sel_w ? underflow_zeros_w : exp_result_w;
wire [16:0] e1_w = (~ wire_b1_prod_result[33:17]);

wire  [33:0]   wire_q_partial_0_result;
`ifdef isISE
mul17x17u1c   q_partial_0( 
  .clk(clock),
  .a(wire_a1_prod_result[34:18]),
  .b(e1_w),
  .p(wire_q_partial_0_result)
);
`endif

`ifdef isALTERA
lpm_mult   q_partial_0
( 
  .aclr(aclr),
  .clken(clk_en),
  .clock(clock),
  .dataa(wire_a1_prod_result[34:18]),
  .datab(e1_w),
  .result(wire_q_partial_0_result)
);
defparam
  q_partial_0.lpm_pipeline = 1,
  q_partial_0.lpm_representation = "UNSIGNED",
  q_partial_0.lpm_widtha = 17,
  q_partial_0.lpm_widthb = 17,
  q_partial_0.lpm_widthp = 34,
  q_partial_0.lpm_type = "lpm_mult",
  q_partial_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
`endif

reg	[16:0]	e1_dffe_2;
reg	b_is_infinity_dffe_2;
reg	divbyzero_pipe_dffe_2;
reg	a_is_infinity_dffe_2;
reg	a_zero_b_not_dffe_2;
reg	nan_pipe_dffe_2;
reg	over_under_dffe_2;
reg	[7:0]	exp_result_dffe_2;
reg	sign_pipe_dffe_2;
reg	[49:0]	remainder_j_dffe_2;
reg	[33:0]	b1_dffe_2;
always @ (posedge clock)begin
  e1_dffe_2 <= e1_w;
  b_is_infinity_dffe_2 <= b_is_infinity_dffe_1;
  divbyzero_pipe_dffe_2 <= divbyzero_pipe_dffe_1;
  a_is_infinity_dffe_2 <= a_is_infinity_dffe_1;
  a_zero_b_not_dffe_2 <= a_zero_b_not_dffe_1;
  nan_pipe_dffe_2 <= nan_pipe_dffe_1;
  over_under_dffe_2 <= overflow_underflow;
  exp_result_dffe_2 <= wire_exp_result_muxa_dataout;
  sign_pipe_dffe_2 <= sign_pipe_dffe_1;
  remainder_j_dffe_2 <= {wire_a1_prod_result[34:0], {15{1'b0}}};
  b1_dffe_2 <= wire_b1_prod_result;
  //wire_q_partial_0_result
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

wire  [50:0]   wire_remainder_mult_0_result;
`ifdef isISE
mul34x17u1c   remainder_mult_0( 
  .clk(clock),
  .a(b1_dffe_2),
  .b(wire_q_partial_0_result[32:16]),
  .p(wire_remainder_mult_0_result)
);
`endif

`ifdef isALTERA
lpm_mult   remainder_mult_0
( 
  .aclr(aclr),
  .clken(clk_en),
  .clock(clock),
  .dataa(b1_dffe_2),
  .datab(wire_q_partial_0_result[32:16]),
  .result(wire_remainder_mult_0_result)
);
defparam
  remainder_mult_0.lpm_pipeline = 1,
  remainder_mult_0.lpm_representation = "UNSIGNED",
  remainder_mult_0.lpm_widtha = 34,
  remainder_mult_0.lpm_widthb = 17,
  remainder_mult_0.lpm_widthp = 51,
  remainder_mult_0.lpm_type = "lpm_mult",
  remainder_mult_0.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";

`endif

reg	[16:0]	e1_dffe_3;
reg	[49:0]	remainder_j_dffe_3;
reg	sign_pipe_dffe_3;
reg	[7:0]	exp_result_dffe_3;
reg	over_under_dffe_3;
reg	nan_pipe_dffe_3;
reg	a_zero_b_not_dffe_3;
reg	a_is_infinity_dffe_3;
reg	b_is_infinity_dffe_3;
reg	divbyzero_pipe_dffe_3;
reg	[16:0]	quotient_j_dffe_3;
always @ (posedge clock)begin//
  e1_dffe_3 <= e1_dffe_2;
  remainder_j_dffe_3 <= remainder_j_dffe_2;
  sign_pipe_dffe_3 <= sign_pipe_dffe_2;
  exp_result_dffe_3 <= exp_result_dffe_2;
  over_under_dffe_3 <= over_under_dffe_2;
  nan_pipe_dffe_3 <= nan_pipe_dffe_2;
  a_zero_b_not_dffe_3 <= a_zero_b_not_dffe_2;
  a_is_infinity_dffe_3 <= a_is_infinity_dffe_2;
  b_is_infinity_dffe_3 <= b_is_infinity_dffe_2;
  divbyzero_pipe_dffe_3 <= divbyzero_pipe_dffe_2;
  quotient_j_dffe_3 <= wire_q_partial_0_result[32:16];
  //wire_remainder_mult_0_result
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------


wire  [49:0]  wire_remainder_sub_0_result = {remainder_j_dffe_3[49:15], {15{1'b0}}} - wire_remainder_mult_0_result[49:0];

wire  [33:0]   wire_q_partial_1_result;
`ifdef isISE
mul17x17u1c   q_partial_1( 
  .clk(clock),
  .a(wire_remainder_sub_0_result[35:19]),
  .b(e1_dffe_3),
  .p(wire_q_partial_1_result)
);
`endif

`ifdef isALTERA
lpm_mult   q_partial_1
( 
  .aclr(aclr),
  .clken(clk_en),
  .clock(clock),
  .dataa(wire_remainder_sub_0_result[35:19]),
  .datab(e1_dffe_3),
  .result(wire_q_partial_1_result)
);
defparam
  q_partial_1.lpm_pipeline = 1,
  q_partial_1.lpm_representation = "UNSIGNED",
  q_partial_1.lpm_widtha = 17,
  q_partial_1.lpm_widthb = 17,
  q_partial_1.lpm_widthp = 34,
  q_partial_1.lpm_type = "lpm_mult",
  q_partial_1.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";

`endif

reg	sign_pipe_dffe_4;
reg	[7:0]	exp_result_dffe_4;
reg	over_under_dffe_4;
reg	nan_pipe_dffe_4;
reg	a_zero_b_not_dffe_4;
reg	a_is_infinity_dffe_4;
reg	b_is_infinity_dffe_4;
reg	divbyzero_pipe_dffe_4;
reg	[16:0]	quotient_k_dffe_4;
always @ (posedge clock)begin//
  sign_pipe_dffe_4 <= sign_pipe_dffe_3;
  exp_result_dffe_4 <= exp_result_dffe_3;
  over_under_dffe_4 <= over_under_dffe_3;
  nan_pipe_dffe_4 <= nan_pipe_dffe_3;
  a_zero_b_not_dffe_4 <= a_zero_b_not_dffe_3;
  a_is_infinity_dffe_4 <= a_is_infinity_dffe_3;
  b_is_infinity_dffe_4 <= b_is_infinity_dffe_3;
  divbyzero_pipe_dffe_4 <= divbyzero_pipe_dffe_3;
  quotient_k_dffe_4 <= quotient_j_dffe_3;
  //wire_q_partial_1_result
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
wire [22:0]  man_zeros_w = {23{1'b0}};
wire round_bit = wire_q_partial_1_result[21];
wire guard_bit = wire_q_partial_1_result[22];
wire [4:0]  sticky_bits = |wire_q_partial_1_result[20:16];
wire quotient_process_cin_w = (round_bit & (guard_bit | sticky_bits[4]));
wire [30:0] wire_quotient_process_result = {quotient_k_dffe_4, {14{1'b0}}} + {{14{1'b0}}, wire_q_partial_1_result[32:22], {6{1'b1}}} + quotient_process_cin_w;
wire man_result_mux_select = (over_under_dffe_4 | a_zero_b_not_dffe_4 | nan_pipe_dffe_4 | b_is_infinity_dffe_4 | a_is_infinity_dffe_4 | divbyzero_pipe_dffe_4);
wire [22:0] wire_man_result_muxa_dataout = man_result_mux_select ? {nan_pipe_dffe_4, man_zeros_w[21:0]} : wire_quotient_process_result[28:6];
always @ (posedge clock)begin//
  result <= {sign_pipe_dffe_4, exp_result_dffe_4, wire_man_result_muxa_dataout};
end

endmodule